Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, Ultrabooks™, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology).
In a computer platform, both a processor's voltage regulator and a platform power supply have peak instantaneous power delivery constraints to be managed in order to ensure stable operation. In some systems, each individual voltage regulator is sized for peak power consumption of individual voltage rails such as processor cores and graphics engines. Similarly, the platform power supply is sized for the peak power demand of the sum of all voltage rails. Yet sizing the input power delivery system (including platform power supply) to supply the sum of peak power on all voltage rails is a significant over-design of real peak power demand during real workload operation.
However, allocating power to individual rails using a fixed allocation scheme can result in significant performance losses as workload power delivery demand on each rail shifts. Furthermore, on a processor with a single input voltage rail and several on-die integrated voltage rails, there is not an easy option to manage allocation of peak power to each of the on-die voltage rails.